PICMG 2.16 Tutorial
Summary | Introduction | Evolution | Limitations of the PCI Bus | Time-to-Market
Specification Detail | Fabric and Node Slots | Key Features Summary | Applications
Related Specifications | Additional Information
The proliferation of IP/Ethernet-based communications, the ongoing need for increased bandwidth, and constant time-to-market pressures have telecom and datacom integrators looking for next-generation platforms and solutions that will keep them at pace with today's evolving and emerging networks.
The PICMG 2.16 specification, or CompactPCI Packet Switching Backplane (cPSB), has been designed with these needs in mind as it builds upon the CompactPCI platform to include dual switched 10/100/1000 Ethernet fabrics.
The specification has acquired rapid acceptance because it blends the robustness, reliability and hot-swap capabilities inherent with CompactPCI with the ubiquity of Ethernet - yielding an architecture better suited for high availability and next-generation network applications.
PICMG 2.16, or CompactPCI Packet Switching Backplane, is one of the newer specifications issued by the PCI Industrial Computer Manufacturers Group (PICMG). PICMG 2.16 is an extension of the PICMG 2.x family of specifications that implements a packet-based switching architecture (based on Ethernet) on top of CompactPCI.
This enables elements in a chassis to be considered "network elements" as opposed to the master/slave structure in the traditional, bus-based CompactPCI architecture.
The spec, co-sponsored by PT, was ratified on September 5, 2001 in just under a year of development. This fast track to ratification was enabled by a team of over 70 companies; chaired by PTs' John Peters. Joe Muczynski, also of PT, acted as co-secretary/editor.
It was one of the most anticipated specs in recent history, and within 18 months over 40 companies were producing and shipping PICMG 2.16 compatible products.
PICMG 2.16 is an open specification supported by the PCI Industrial Computer Manufacturers Group. The CompactPCI Packet Switching Backplane sub-committee maintains this specification. For information on how to become a member of the sub-committee, contact PICMG.
The PICMG 2.16 platform evolved from the confluence of new IP-based communication applications, the growing popularity of CompactPCI and the fact that IP Ethernet switching has become the dominant LAN topology in the enterprise marketplace.
Its necessity, however, was driven by the before mentioned and ever-present need for bandwidth and time-to-market pressures - both inherent limitations of the PCI bus.
Although PICMG 2.16 has been designed to conquer the limitations of the PCI bus, this new architecture is designed to complement existing CompactPCI systems, not replace them - thus extending the life of the rugged and familiar CompactPCI architecture.
Limitations of the PCI Bus
CompactPCI has some inherent shortcomings that had to be addressed for next-generation applications.
First, the PCI bus is a shared bus architecture with a theoretical throughput limitation of 533MB/sec over only five slots. This performance is far below even moderate Ethernet capabilities.
Also, drivers compatible with the operating system (OS) installed in the slot-one controller must be in each chassis unit. Although many capable CompactPCI subsystems are available, vendor selection and system capabilities generally are limited when developing a product based on a preferred OS. And the lack of an appropriate driver for a component will delay development pending completion and debugging of the OS-specific driver.
Meantime, standard CompactPCI subsystems have only a single CompactPCI bus interface, so the entire system becomes inoperable if the interface controller on one subsystem seizes the bus, meaning a single point of failure can stop a system. While a level of resilience can be provided (at a higher cost) by redundant CompactPCI buses on the same mid-plane, chassis-width and speed limits imposed by CompactPCI remain unavoidable obstacles.
Another major factor in developing the PICMG 2.16 spec was the need to reduce integration time. With time-to-market so critical in today's fast-paced, high-tech industry, something had to be done. In a 2.16 system, development occurs at the Network/Transport level, NOT at the Link (driver/backplane) level. This drastically reduces integration time - while increasing system scalability, reliability and performance.
PICMG 2.16 has been designed to vastly increase inter-board communication capabilities of subsystems within the chassis by moving data off the shared bus architecture of CompactPCI and onto a high availability, high speed, switched 10/100/1000 Ethernet based network topology.
This enables all slots within the chassis to be interconnected by a deterministic, reliable and scalable point-to-point embedded network based on already established enterprise network industry standards/protocols. Using PICMG 2.16, throughput can be improved under some applications by as much as an order of magnitude, without affecting the legacy components or behavior of the shared CompactPCI bus.
There are two concepts underlying PICMG 2.16.
- An Ethernet infrastructure is embedded in the CompactPCI midplane, accessed via the J3 connector. An Ethernet switching element will reside in one or more of the CompactPCI slots, interconnecting all the slots in the chassis.
- All subsystems will operate as stand-alone "systems on a card" interfacing with each other through a network stack on top of Ethernet.
With these two underlying concepts, PICMG 2.16 offers the following benefits:
- Increased performance/throughput
- Architectural scalability/unlimited "virtual backplanes"
- Increased reliability/backplane redundancy
- Decreased-time to-market
Keep in mind that while PICMG 2.16 radically improves performance, scalability and reliability of CompactPCI, it preserves its mechanical, power and hot-swap attributes. PICMG 2.16 also leaves intact the H.110 telephony bus for systems supporting that standard. Components that support PICMG 2.16 for communications within the same chassis also can also be mixed with units relying on the CompactPCI bus. Because there is no need to change out subsystems built around legacy CompactPCI elements, developers can gradually grow systems capabilities seamlessly onto the PICMG 2.16 framework. This means that systems can be evolved in response to changing needs, without scrapping prior design work.
Because of the nature of a Packet Switching Backplane the PICMG 2.16 specification adds Fabric and Node slot definitions to the standard CompactPCI System and Peripheral slot definitions. By combining Fabric, Node, System, and Peripheral capabilities, the Packet Switching Backplane supports many more applications than the standard CompactPCI backplane.
Fabric slots are the one or two slots in a chassis that switch packets between the Node slots (up to two Fabric slots may be supported in a 19 inch cPCI chassis). Each Fabric slot may support from one to twenty Node slots (see below) & 10/100/1000 Mbits and connection to the packet-switched backplane is done via 10-200 J3/J5 pins. Fabric slots are hot-swappable and the available bandwidth for each can be up to 2.5 Gbytes/sec.
P5 Fabric Slot Detail
P3 Node Slot Detail
P5 Fabric Slot Detail
Node slots are the remaining slots in the chassis that are attached/linked to one or both of the fabric slots (up to twenty Node slots may be supported in a 19 inch CompactPCI chassis). Any Node slot may support one or two PICMG 2.16 buses (Fabric slots) & 10/100/1000 Mbits and connection to the Packet Switching Backplane is done via 10 or 20 J3 pins. Node slots are hot-swappable and the available bandwidth for each can be up to 500 Mbytes/sec.
P1-P5 Node Slot
P3 Node Slot Detail
Increased inter-board communication: All sub-systems will operate as stand-alone "systems on a card" interfacing with each other through a network stack on top of Ethernet.
Standards-based architecture: Standards-based architectures like PICMG 2.16 enable engineers to develop solutions in a shorter time, with a lower total cost of ownership - allowing them to focus on their core competencies. For many equipment developers, this has become the 'software applications and operating environment' that make their product unique.
Increased throughput/density/performance: Offers throughput rates up to 40Gbit/sec full duplex, more than an order-of-magnitude improvement over CompactPCI implementations.
Decreased time-to-market: Because PICMG 2.16 leverages existing CompactPCI and Ethernet technology, design engineers can quickly implement a 2.16 design without extreme changes to development techniques or system footprint.
Reduced integration time: Development occurs at the network/transport layer, NOT at the link (driver/backplane) level. This drastically reduces integration time - while increasing system scalability, reliability and performance.
Increased scalability: Unlimited "virtual backplanes."
Increased reliability: The platform accommodates two fully redundant networks within a single chassis, potential system losses are limited to a single slot in a chassis - the ultimate hot-swap failsafe. Also, cables and connectors, the LAN elements most prone to failure, are eliminated - creating a more reliable network.
Leverages ubiquity of Ethernet: Ethernet is everywhere. 95 percent of world-wide data travels on Ethernet. 85 percent of installed networks are Ethernet. And Ethernet technology continues to be incorporated into more product than ever before.
Discrete VoIP Media Gateway Architecture (de-centralized management/HA)
Integrated Access Device (centralized management/non-HA)
IP DSLAM Architecture (de-centralized management/non-HA)
Server Clustering Architecture (de-centralized management/non-HA)
Server Clustering Architecture (de-centralized management/non-HA)
CompactTCA uses the CompactPCI mechanicals and bundles many of the fragmented specs found in the PICMG 2.x family. The objective is to clearly define an embedded system platform specification.
The key element of the CompactTCA specification is that it retains compatibility with most existing CompactPCI/PICMG 2.16 products.
The proposed CompactTCA architecture complements AdvancedTCA by featuring PICMG 2.16 packet switching as the primary interconnect, mandatory system management and elimination of the PCI bus for data transfer. Much like PICMG 2.16, CompactTCA is expected to be an "edge-level" technology.
AdvancedTCA is a completely new architectural design with a focus on telecommunications applications.
AdvancedTCA was recently ratified as a standard in December of 2002. With a much larger overall form factor and less granularity at the board level, it is anticipated that AdvancedTCA will complement other standards-based architectures, like PICMG 2.16 and CompactPCI, by offering an alternative to non-proprietary architectures. Because of its size and functions, it most likely will be adopted as a "core-level" technology versus an edge level technology. Core applications require extremely high bandwidth and are less affected by cost.